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2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
AC and DC Logic Input Measurement Levels for Differential
Signals
Figure 86: Single-Ended Requirements for Differential Signals
V DDCA or V DDQ
V SEH(AC)
V SEH(AC)min
V DDCA /2 or V DDQ /2
CK or DQS
V SEL(AC)max
V SEL(AC)
V SSCA or V SSQ
Time
Note that while CA and DQ signal requirements are referenced to V REF , the single-ended
components of differential signals also have a requirement with respect to
V DDQ /2 for DQS, and V DDCA /2 for CK.
The transition of single-ended signals through the AC levels is used to measure setup
time. For single-ended components of differential signals, the requirement to reach
V SEL(AC)max or V SEH(AC)min has no bearing on timing. This requirement does, however,
add a restriction on the common mode characteristics of these signals (see Table 63
(page 119) for CK/CK# single-ended requirements, and Table 65 (page 119) for DQ and
DQM single-ended requirements).
Table 68: Single-Ended Levels for CK, CK#, DQS, DQS#
LPDDR2-1066 to LPDDR2-466
LPDDR2-400 to LPDDR2-200
Symbol
Parameter
Min
Max
Min
Max
Unit Notes
V SEH(AC)
Single-ended HIGH
(V DDQ /2) + 0.220
Note 1
(V DDQ /2) + 0.300
Note 1
V
2, 3
level for strobes
Single-ended HIGH
(V DDCA /2) + 0.220
Note 1
(V DDCA /2) + 0.300
Note 1
V
2, 3
level for CK, CK#
V SEL(AC)
Single-ended LOW
Note 1
(V DDQ /2) - 0.220
Note 1
(V DDQ /2) + 0.300
V
2, 3
level for strobes
Single-ended LOW
Note 1
(V DDCA /2) - 0.220
Note 1
(V DDCA /2) + 0.300
V
2, 3
level for CK, CK#
Notes:
1. These values are not defined, however, the single-ended signals CK, CK#, DQS0, DQS#0,
DQS1, DQS#1, DQS2, DQS#2, DQS3, DQS#3 must be within the respective limits
(V IH(DC)max / V IL(DC)min ) for single-ended signals, and must comply with the specified limi-
tations for overshoot and undershoot (see Figure 91 (page 130)).
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
125
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
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